Processors of today are broadly divided into a processor for a PC/server placing the top priority on performance and an embedded processor requested to satisfy both high efficiency and high performance. As an embedded processor requested for high efficiency, an embedded processor of an RISC (Reduced Instruction Set Computer) type using a 16-bit fixed-length instruction set capable of realizing high code efficiency is widespread. The high code efficiency is indispensable for effective utilization of an on-chip cache, a RAM, and a ROM even at present when the capacity of an off-chip memory is large. With the 16-bit fixed-length instruction set, although the program size can be decreased, the number of instructions increases. In particular, due to constraints on operand assignment, the number of instructions in transfer between registers and immediate value transfer instructions increases. Source forwarding is also generally used which forwards a value of a transfer-source register in place of that of a transfer-destination register in order to hide latency of increased transfer instructions. Increase in the number of instructions may cause deterioration in performance and increase in power. The source forwarding that compensates deterioration in performance is one of causes decrease in operation frequency and increase in power due to increase in a critical path and a logic scale.
Such a problem is caused by the fact that the instruction code space of the 16-bit fixed-length instruction set is 216 B=64 kB which is much smaller than the instruction code space of 232 B=4 GB of a 32-bit fixed-length instruction set. Consequently, for example, in an ARM Thumb-2 instruction set of non-patent document 1, the instruction code space is extended by mixing 16-bit fixed-length instructions and 32-bit fixed-length instructions. On the other hand, in the processor of the patent document 1, by adding 16-bit prefixes to the 16-bit fixed-length instruction set, the instruction code space is extended. The prefix denotes an instruction code having the function of changing the meaning of a subsequent instruction code or adding information to a subsequent instruction code. A prefix itself does not become an instruction. The prefix was used by the i386 processor of Intel Corp. announced in 1985 when the 16-bit architecture was changed to the 32-bit architecture while maintaining upward compatibility and has been known for 20 years or more. In the i386 processor, a prefix is used to change the meaning of the operand size of a subsequent instruction code. Since all of the i386 processor and subsequent machines are processors of the CISC (Complicated Instruction Set Computer) type using a variable length instruction set, an instruction decoding circuit is originally complicated, so that it can be said that the influence on a realization circuit accompanying addition of a prefix is relatively small.
The prefixes in the patent document 1 are used to make a 3-operand instruction by adding an operand to a 2-operand instruction, to add an index to a register indirect addressing instruction to obtain a register relative indirect addressing instruction, and to change a source operand of a 2-operand modify-type instruction to a 3-operand instruction. The patent document 1 discloses a realization method using, as an example, a scalar processor for decoding an instruction code by 16 bits. Since a prefix is also one instruction code, it takes two cycles to decode an instruction with a prefix, and also takes two cycles for execution.
Patent document 2 discloses a processor obtained by improving the processor of the patent document 1. The disclosed functions of a prefix are a change of a destination operand of a 2-operand modify-type instruction to a 3-operand type and extension of bit width of a literal operand. By simultaneously performing decoding of a prefix and a preceding instruction in the decoding of an instruction with a prefix which takes two cycles in the patent document 1, the cycle of decoding the prefix is hidden to thereby realize one cycle execution of the instruction with the prefix.
One of methods of handling the problem such that a resister assignment field cannot be assured in a 16-bit fixed-length instruction set is implicit fixed register assignment. In SH-4A described in non-patent document 2, an instruction using R0 as one of 16 general registers as an implicit fixed register is defined. By utilizing such an instruction by preferentially allocating R0 to an implicit fixed register using instruction at the time of register allocation of a compiler, a demerit of a fixed register is lessened. However, decrease in flexibility of register allocation by fixed operand assignment cannot be always sufficiently hidden. In particular, a provider of a compiler for a plurality of processors for dealing various instruction set architectures by the same compile method has strong tendency of not using an advantage of a specific architecture. Consequently, there is a case that utilization of a fixed register using instruction is insufficient. That is, it cannot be said that a fixed register using instruction is a sufficient countermeasure against the problem such that a register assignment field cannot be assured, and further improvement is necessary.    Non-patent document 1: Markus Levy, “ARM Grows More Thumbs,” Microprocessor Report, Jun. 17, 2003-02, June 2003    Non-patent document 2: SH-4A software manual, Internet URL http://documentation.renesas.com/jpn/products/mpumcu/rjj09b 0090_sh4a.pdf, p. 3-9 to p. 3-19, Tables 3.4, 3.5, 3.6, 3.9, 3.10, and 3.13 (SH-4A Software Manual, Internet URL http://documentation.renesas.com/eng/products/mpumcu/rej09b 0003_sh4a.pdf, pp. 33-42, Tables 3.4, 3.5, 3.6, 3.9, 3.10, and 3.13)    Patent document 1: Japanese Unexamined Patent Publication No. 2000-284962    Patent document 2: Japanese Unexamined Patent Publication No. 2004-030015